The present invention relates generally to the field of electronic data processing devices. More particularly, the present invention relates to new processor architecture and algorithms for non-volatile memory updates.
In any computer system it is extremely important to protect the boot code that is contained in the non-volatile read only memory (ROM) from being accidentally erased. If ROM boot code is destroyed, the machine will not even boot to an operating system making recovery almost impossible. Since today""s machines use small flash ROM packages the end user can not recover a system that has lost its ROM data because the ROM component can not be replaced by the end user. All this means is that a software virus attack that destroys boot ROM code is entirely unacceptable. Hence it is necessary to have a full guarantee that boot ROM code is protected by the virtue of design and yet is updatable to a newer valid firmware. It is also necessary in a multiprocessor system that one processor execute the flash ROM update and other processors are in rendezvous state while a valid update is being processed.
In the prior art of 32 bit processors, on chip micro-code is generally provided with a patching facility. Unfortunately, this prior art method is unsuitable in the case of successive generation 64 bit processors which no longer possess the prior art micro-code patching facility. Also, the prior art micro-code patching facility is useful only to embed a 2 kilo-byte (KB) patch into ROM and is unable to perform an update of 1 mega-byte (MB) or greater.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop improved methods for updating non-volatile memory in successive processor generations.
A novel processor architecture and algorithms are provided which improve non-volatile memory binary code updates and increase processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM.
The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory update includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is then used to call a specific non-volatile memory implementation routine.